The present invention relates to a static random access memory (xe2x80x9cSRAMxe2x80x9d hereinafter) and a semiconductor device.
By virtue of the progress of microfabrication technology, the operation speed and the integration degree of LSIs (Large Scale Integrated Circuits) have been increasing in recent years. In order to put an LSI that operates at high speed into practical use, the reduction in consumption of power of the LSI is one of important technical requirements. That is, generally, the consumption of power increases when an LSI is operated at high speed. Therefore, in order to stably operate the LSI, a ceramic package and radiator fins and so on are needed, resulting in an increased cost. In recent years portable devices have been advancing toward further reduction in size and weight, and the reduction in consumption of power is important also in achieving the long-time use of the devices on batteries as well.
Conventionally, an SRAM cell constructed of four N-type MOS (Metal-Oxide Semiconductor) transistors and two P-type MOS transistors has generally been used. FIG. 9 shows a circuit diagram of a conventional SRAM cell constructed of four N-type MOS (xe2x80x9cNMOSxe2x80x9d hereinafter) transistors and two P-type MOS (xe2x80x9cPMOSxe2x80x9d hereinafter) transistors. FIG. 10 shows the layout of the whole SRAM that employs the SRAM cells having the above construction.
Referring to FIG. 10, the SRAM 1 is constructed roughly of an input/output interface section 2, a memory section 3 through which the SRAM cells are spread, an address decoder section 4 and a data write/read control section 5. The SRAM cells that constitute the memory section 3 have the construction shown in FIG. 9. That is, a bit line B is connected to the source (drain) of a first NMOS transistor 11. A word line WL is connected to the gates of the first NMOS transistor 11 and a second NMOS transistor 12. An inverted bit line BX is connected to the source (drain) of the second NMOS transistor 12.
A drain (source) Y that belongs to the first NMOS transistor 11 and is not connected to the bit line B is connected to the gates of a third NMOS transistor 13 and a first PMOS transistor 15 and further connected to the drains of a fourth NMOS transistor 14 and a second PMOS transistor 16.
A drain (source) XY that belongs to the second NMOS transistor 12 and is not connected to the inverted bit line BX is connected to the gates of the fourth NMOS transistor 14 and the second PMOS transistor 16 and further connected to the drains of the third NMOS transistor 13 and the first PMOS transistor 15.
The sources of the third NMOS transistor 13 and the fourth NMOS transistor 14 are connected to GND, while the sources of the first PMOS transistor 15 and the second PMOS transistor 16 are connected to VDD.
In the above arrangement, semiconductor regions in which a channel is formed when each of the first NMOS transistor 11 through fourth NMOS transistor 14 is turned on are connected to GND. On the other hand, other semiconductor regions in which a channel is formed when each of the first PMOS transistor 15 and the second PMOS transistor 16 is turned on are connected to VDD.
However, the above conventional SRAM has the following problems. That is, in accomplishing a reduced power consumption of the SRAM, a great effect can be obtained by lowering the operating voltage (VDD). However, if the voltage VDD is lowered, then the driving current of the MOS transistors becomes so small that delay time of the circuit disadvantageously increases, resulting in the reduction of the operating speed. As a solution to this problem, it is conceivable to reduce the threshold voltage (Vth) of each MOS transistor such that the driving current of the MOS transistor is not reduced much even with a low voltage. However, if the threshold voltage Vth is reduced, then a leak current of the MOS transistor increases, and this leads to the problem that the power consumption increases great due to the existence of the leak current even in a standby mode.
Accordingly, an object of the present invention is to provide an SRAM and a semiconductor device that are each able to operate on a low voltage so as to consume very little power and that each have a small area.
In order to accomplish the above object, according to an aspect of the present invention, there is provided a static random access memory (SRAM) comprising MOS transistors which each include a channel-forming semiconductor region and a gate electrically connected with each other.
The MOS transistor whose gate is electrically connected with the channel-forming semiconductor region is referred to as xe2x80x9cDTMOS (Dynamic Threshold MOS) transistorxe2x80x9d or simply xe2x80x9cDTMOSxe2x80x9d herein. Because the gate is electrically connected with the channel-forming semiconductor region in the DTMOS transistors, each MOS transistor is controllable to have a low threshold voltage |Vth| in its ON stage and a high threshold voltage |Vth| in its OFF stage. This enables a low-voltage operation at 0.5 V and prevents leak current in the OFF stage from increasing. Thus, the SRAM of the present invention is allowed to consume less power than the conventional SRAM. Furthermore, because |Vth| of the DTMOS in the ON stage is low, the ON-state resistance is also small, and it is possible to increase the writing/reading speed. If the writing/reading speed for the DTMOS is maintained equivalent to the conventional speed, then it is possible to narrow the gate width to the extent according to a decrease of the ON-state resistance to thereby achieve the reduction in area of the SRAM.
In one embodiment, memory cells of the SRAM of the invention include N-type MOS transistors formed of DTMOS, and P-type MOS transistors having a channel-forming semiconductor region electrically connected with a power source.
According to the above construction, the N-type MOS transistors included in the memory cells or SRAM cells are DTMOS transistors. This allows the low-voltage operation, low consumption of power and high writing/reading speed of the SRAM cells. If the writing/reading speed is maintained equivalent to the conventional speed, then the reduction in area of the SRAM cells is achieved.
The PMOS transistors may have a gate oxide film larger in thickness than the N-type MOS semiconductor transistors.
In this case, because the ON-state resistance of the P-type MOS transistors increases, the current decreases, allowing the NMOS transistors to be constructed in a smaller size. Therefore, it is possible to achieve a further reduction in area, a small leak current and a low consumption of power of the SRAM cells.
The channel-forming semiconductor region of each P-type MOS transistors may be formed of an N-type well deeper than a P-type well that forms the channel-forming semiconductor region of the N-type MOS transistor, and these channel-forming semiconductor regions are electrically isolated from each other.
In this case, no shallow wells, which need to be isolated from each other, are used for the P-type MOS transistors. Thus, the area of each SRAM cell decreases by that much.
In the above embodiment, the PMOS transistors of the memory cells can be replaced with resistors.
In one embodiment, the SRAM of the invention comprises write circuit means that include DTMOS transistors.
As described above, the DTMOS transistors have a low ON-state resistance and are able to suppress the leak current in the OFF stage. Therefore, the lower voltage operation, lower consumption of power, higher writing speed and size reduction of the write circuit are achieved.
In one embodiment, the DTMOS transistors of the write circuit include N-type DTMOS transistors which serve to make a bit line and an inverted bit line have a high-level electric potential, respectively.
In this case, at the time of writing to the memory cells, the high-level potentials of the bit line and the inverted bit line are reduced. Thus, a further reduction in consumption of power is achieved.
The SRAM of the invention may comprise read circuit means that includes DTMOS transistors.
Furthermore, according to another aspect of the present invention, there is provided a semiconductor device, comprising:
first MOS transistors for performing internal processing, which each have a channel-forming semiconductor region formed of a first well; and
second MOS transistors for performing direct signal transmission and reception to and from an external device, which each have a channel-forming semiconductor region formed of a second well deeper than the first well.
The semiconductor device with this construction is a highly reliable semiconductor device with a high electrostatic withstand voltage.